Technique for the conversion to digital form of interspersed symbolic and graphic data

ABSTRACT

A system for computerizing changes to engineering drawings by separating graphical and textual information in a digital representation of a drawing so that desired changes can be made to the digital representation. Separation is accomplished by scanning the document and analyzing it element by element until all objects have been separated one from another. Special purpose circuitry is provided to test for connectivity between one state bits in a single row and adjacent one state bits in the directly neighboring row.

United States Patent [191 Cobb et al.

[ Apr. 16, 1974 TECHNIQUE FOR THE CONVERSION TO DIGITAL FORM OFINTERSPERSED SYMBOLIC AND GRAPHIC DATA [75] Inventors: Richard O. Cobb;Albert C. Moore,

both of Poughkeepsie, NY.

[73] Assignee: International Business Machines Corporation, Armonk, NY.

[22] Filed: Apr. 30, 1971 [21] Appl. No.: 139,113

[52] U.S. Cl. 340/l46.3 H, 340/146.3 AG [51] Int. Cl. G06k 9/12 [58]Field of Search 340/1463 [56] References Cited UNITED STATESPATENTS3,564,498 2/1971 Stern 340/1463 3,196,398 7/1968 Baskin 340/14633,496,543 2/1970 Greenly 340/1463 H 3,234,513 2/1966 Brust 340/1463 AG3,297,993 1/1967 Clapper 340/1463 .1 3,496,542 2/1970 Rabinow 340/l46.3AG

3,588,822 6/1971 Yamamoto 340/1463 .1

OTHER PUBLICATIONS S. H. Unger, Pattern Detection and Recognition, April30, 1959, Proceedings of the IRE, pp. 1737 to 1751. I

Primary ExaminerPaul J. Henon Assistant Examiner-Robert F. GnuseAttorney, Agent, or Firm-Charles E. Rohrer; Charles E. Rohrer [57]ABSTRACT A system for computerizing changes to engineering drawings byseparating graphical and textual information in a digital representationof a drawing so that desired changes can be made to the digitalrepresentation. Separation is accomplished by scanning the document andanalyzing it element by element until all objects have been separatedone from another. Special purpose circuitry is provided to test forconnectivity between one state bits in a single row and adjacent onestate bits in the directly neighboring row.

4 Claims, 23 Drawing Figures PATENTEIIAPR I 6 I974 SIIEEI O1 OF 20 UPCONNECTIONS TO CURRENT SPAN ONTO CURRENT SPAN WN CONNECTIONS TO CURRENTSPAN BIT REMAINING IN IMAGE ID= BIT ERASED FROM IMAGE INITIAL SPAN II(III ISIIIIIIIIIITI IVIIIIIIIIII IwIIIIIIII I (Z) I l T INVENTORS'RICHARD o. COBB ALBERT c. MOORE BY M Z vA I WV! VTH UR I DI nhflNI 80 VVA U s 0 AC RIL N N N N N 0 N MN I 1 AA A A A I DID! DI DI DIP I Mm DIDImm NH 5 S s SS 8 S OM S 58 I I I I ILF 07 K JD Z Q Z I I T H I I K T XTTT T I T I: N N N N N N N N H N D EE E CL EE IE CL GI E C B7 MM M M MM MM I M A I [LE CLT ELT E TE rrII E T ..N ILL LNLNLL L ..N I I E ELELELECLELCLCL EL EL IJ EI. M M M M I T C G G TIC G C EL CL CL CE C S s S SS S IIJ J IJ B B B 0 0 O ATTORNEY PATENTEDAPRTS AAAA 3.805.237 SHEET 02W 20 MAIN DOCUMENT STORAGE \600 SCAN CHANNEL DATA SEPARATOR CONTROL 400200 300 W 101\ soo A DDDDMEAAT Too F|G 3 GRAPHIC DATA 108 4 4 1 A02ALPHANUMERIC DATA AAPDT VA405 D l A05 406 109 AA T T T I A 'EDMEDTOEMAGE 104 ADT TAD A/ A A A OBJECT AMAGE 7 2 2 I A D c D E F H 3 AAAPDTEMAGE \4 4 4 A AA AA A SEGMENT IMAGE 4 H2 A T A A OBJECT IMAGE 4 4 G H IJ A OBJECT DATA OBJECT DATA SEPARATED SEPARATED (GRAPHIC) (ALPHANUMERIC)PATENTED APR 1 6 B74 SHEET 0 0F 20 E5 5% w: T

Q ILIZIQlIlZTf GIZEEMEZOZP I z P8228 233 c o -|m r I XAM PATENTEDAPR 161974 SHEET 05 0F 20 2? o 2% E; f

PATENTEDAPRIBO'M 3805237 sum uaurzo F|G.5A 702 DATA BUS CONTROL BUS RBAB A HIFT R ISTER 0 S EG A REGISTER SHIFT TRANSFER CONTROL PATENTEDAPR1s ma SHEET 08 0f 20 B REGISTER 0:5 (FM +1 N F N-H TRANSFER CONTROL CSHIFT REGISTER C SR INDICATOR "ATENTEDAFRJ e 191 FIG.5C

DB REGTSTER D2 SHIFT RB TRANSFER C CONTROL "D OUTPUT GATES SHEET 10 0F20 D SR INDICATOR D SH IFT REG TRANSFER CONTROL :mnmgmrmaam 33305237 sum11'0F20 FIG.5D

SHIFT CONTROL UNIT BINARY COUNTER SPAN START BINARY COUNTER A I REGISTERI OUTPUT GATES FTGSE FIG FIC. FIG. FIG. 5A 5B 5C 5D ATENTEDAFRWISYG3.805237 SHEET 12 0F 20 FIG.6

0C ODD CYCLE I RB H mm ALL RECs LB LOAD REC A COMPARE .B-E- C CA COMPAREB'-C D CB ['1 R EsET REC-C C0 HTRARCEER REC 0 REC C CD Fl sTEP SHIFTCTRL CART CE Fl TEsT CTR FOR 52 RECYCLE uAlTLL CTR :32 DB TEsT CTRPOSITION Co M SHIFT REC C RE(; D

' 00 {"l STEP SHIFT CTRL UNIT RECYCLE UNTIL E |TEST CTR FOR 52 NR :52 IEA IJLISET sTATus INDICATORS INDICATORS R TEIITEIIARRI s RII 3.805237 sIEET 13 (F20 E G I EvEIII CYCLE l 7 R8 H mm ALL REGS LB [1 LOAD REC A LCLOAD REC B AB 1 TEsT REC POSITION A,

AC SHIFT REC A REC F AD 1 sTEP sIIIFT CTRL UNIT AE TEsT CTR FOR 52REGYGLE UNTIL CTR= 52 A BA CCIIRARE. B-F C REGYCLE UNTIL GTR= 32 DB TESTGTR POSITION Go DC SHIFT REG G REG D RECYCLE IIIIITIL CTR=52 EA I 'IsEsTATus INDICATORS FB F'IT'EST REG POSITION Fo FC SHIFT REC F RECYCLEIIIIITIL FE ET R FOR 52 CTR 52 READ OUT STATUS INDICATORS R02 I & I REGR05 READ OUT REG D RAYERYERARRYBRYA 3.80523? SHEET 1B OF. 20

FAG-8A w I FILL INPUT ARRAY I INITIALIZE TOMINUS" AND T0 "PLUS" IALIZEPROGRAM R -P RAM T R M A E E S INITIALIZE CONNECTION LIST POINTE RIMARYOINTS Yo LIST, NOARY POINTS T0 UP LIST; 50mm POINTS TO 0TH ENTRY 0F DOWNA UP LISTS PE ELY MARK BOTH Ll EM |NlTlAL|ZE OUTPUT 8L SEGMENTARRAYS,OBJECT VECTOR LIST & OBJECT 'DATA MOVE ROW Y FROM INPUT 805 ARRAYINTO REG A OF SEPARATOR YES A ALL OBJECTS IN THE INPUT ARRAY HAVE 7 T 5BEEN SEPARA ED SET SOURCE BIT "s" T0 OFF MOVE Row Y @D 1 OF INPUT ARRAYY REG- B 806 START THE SEPARATOR ODD CYCLE INCREMENT Y BY +4 PATENTEDAPRI6 I974 SHEET 15 OF 20 Haas aso READ SEPARATOR REc's II INDICATOR BITSINTO CPU TEMPORARY STORAGE /808 FORM LOGICAL OF REG F & R0

w Y OF S NT ARRAY A STORE m ROW Y 0F SEGMENT ARRAY FORM LOGICAL"AND" OFRON Y OF INPUT ARRAY AND COMPLEMENT REG F STORE RE IN RO 0F INPUT ARRAYIS IBC OR IBD ON YES INCREMENT SECONDARY. LIST BOTTOM POINTER BY I ENTRYSTORE REG F IN ROITIv MATION PART OF BOTTOM SECONDARY LIST RE UE OF Y INY INFORMATION P MARK SECONDARY LIST AS "NOT EMPTY" MOVE REG F FROM CPUSTORAGE INTO REG A OF SEPARATOR MOVE ROW Y I OF INPUT ARRAY IN 0 REG BSTART THE SEPARATOR EVEN CYCLE 852 FIG.8C

READ SEPARATOR REGS R INDICATOR BITS INTO CPU TEMPORARY STORAGE UPDATEOBJECT xmm I UPDAT 0 T XMAX OELETE BOTTOM ENTRY IN FROM X E- ZNX -4PRIMARY & DECREMENT PRIMARY BOTTOM POINTER BYI ENTRY INCREMENT PRIMARYLIST BOTTOM'POINTER BY I ENTRY STORE REG F IN ROW INFORMATION PART OFPRIMARY LIST; STORE Y INY INFORMATION PART MARK THE PRIMARY LIST AS "NOTEMPTY" FORM LOGICAL OR OF SEGMENT ARRAY WITH OUTPUT ARRAY INITIALIZESEGMENT ARRAY TEMPORARY STORAGE INTO SEPARATOR REG A UPDATE OBJECT YMAXOR Y MIN FROM Y FORM Y 1a STORE m Y POTEIITEDAPR I6 I974 7 sum 17 OF 20MOVE TH III INFORMATION PART OF THE OM E IN THE PRIMARY LIST TO A OF SEPR AiIATO HE Y INFORMATION PART TO Y SET THE SOURCE BIT"S" ON MOVE T ANOBJECT HAS BEEN SEPARATED E X Tv OF REG CT N; PL -I IN OBJECT X DOESOBJECT THE ROW INFORMATION MOVE PART E BOTTOM ENTRY OF SECONDARY LIST TOREC A XMI N,XMAX,YMIN, X

MEET POSITIO CRITERIA YES START CASSIFIER "I MOVE THE YINFORMATION PARTTO Y SET THE SOURCE BIT"S "ON IS CLASSIFIER FINISHED SWITCH THE PRIMARY& SECONDARY LIST POINTERS AND EMPTY MARKERS SWITCH THE MEANING OF MOVEOBJECT YMIN T0 Y PATENTEDAPR T6 I874 I FTGBE suit? 18 or 20 UPDATESEGMENT x FROM x UPDATE OBJECT Xm FROM X ADD X AX-T TO OBTAINX UPDATESEGMENT x FROM XM UPDATE OBJECT x FROM x W PDATE SEGMENT X 0R Ym FROM YRESET X AND AX YES DIGI SEGMENT IMAGE CONTAINED SEGMENT ARRAY STORERESULT IN OBJECT VECTOR LIST RESET SEGMENT DATA T Eh v PATENTEDAPRISIHMA 3.805237 A SHEET 19 HF 20 9A CONTROL m EDT TE DE 816 /804 /845 E DOWNF'T ADDREss'T ADDREss'z WINTERS UP F2 ADDRESS} ADDRESS 4 W20 sos Y DOWNYT Y DATA ROW INFORMATION CONNECHON Y 2 Y DATA ROW INFPRMATION LIST T DT YN Y,DATA lRow INFORMATION -\v824 822 [815 UP YT Y DATA ROWINFORMATYON-\8M CONNECTION Y? Y DATA Row YRT RMATTDTY LIST T YR Y DATAlRow INFORMATION Y0 "o" ROW Y|1 INPUT ARRAY I Y T i i i Y32 Y53 0" ROW TSEGMENT T A ARRAY I I I I l I Y32 A

1. Apparatus for determining the connectivity of one state bits in adigital element in a single row to one state bits in the next adjacentrow, said element comprised of a contiguous span of one state bits insaid single row, where connectivity is defined to exist where a onestate bit in said adjacent row directly adjoins a one state bit in saidelement along either a vertical or diagonal axis, said apparatuscomprising a first register means for containing a desired element to beanalyzed for connectivity, a second register means for containing asingle row adjacent to the row containing said desired element,comparator means for simultaneously comparing all bit positions in saidfirst register to corresponding bit positions in said second register todetermine said connectivity and for transmitting a signal correspondingto each bit position in said second register where said connectivity isfound to exist, and a third register means for receiving saidtransmitted signals for simultaneously setting all bit positions in saidthird register to contain one state bits at those bit positions forwhich signals are received from said comparator whereby said thirdregister is caused to contain a bit representation pattern of theconnectivity of a digital element to its next adjacent row.
 2. Theapparatus of claim 1 further including a fourth register means forreceiving signals from said third register means, said signals settingall bit positions in said fourth register to a bit representationpattern of only the rightmost element of the connectivity pattern insaid third register.
 3. A method for determining the connectivity of onestate bits in a digital element in a single row to one state bits in thenext adjacent row, said element comprised of a contiguous span of onestate bits in said single row, where connectivity is defined to existwhere a one state bit in said adjacent row directly adjoins a one statebit in said element along either a vertical or a diagonal axis, saidmethod comprising the steps of writing a desired element to be testedfor connectivity into a first register means, writing a single rowdirectly adjacent to the row containing said desired element into asecond register means, simultaneously comparing all bit positions insaid first register to corresponding bit positions in said secondregister to determine said connectivity, transMitting a signalcorresponding to each bit position in said second register where saidconnectivity is found to exist, and receiving said transmitted signalsfor simultaneously setting all bit positions in said third register tocontain one state bits at those bit positions for which signals arereceived from said comparator, whereby said third register is caused tocontain a bit representation pattern of the connectivity of a digitalelement to its next adjacent row.
 4. The method of claim 3 including theadditional step of writing one state bits into a fourth register meansat bit positions corresponding to the rightmost element of theconnectivity pattern contained in said third register means.